ABSTRACT
This proposal was submitted in response to the solicitation "Nanoscale Science and Engineering" (NSF 00-119). The project addresses the fabrication of quantum scale devices through the combined oxidation and etching of Si/SiGe/Si nanostructured pillars. The project aims to demonstrate the validity of nanoscale computing by developing a process technology to fashion quantum dots of a predictable size, shape and placement, suitable for mass production and simple electrical contact. The project includes specific strategies and processes to control the size and composition of the nanostructured pillars and the resulting quantum dots and oxide insulators to be formed. The research spans issues of materials science, circuits, and device fabrication and characterization; the structures to be fabricated are closely integrated with quantum level devices necessary for cellular automata circuits. Methods of high speed testing to characterize the devices as well as theoretical modeling to optimally design the structures are included. The project is highly collaborative between Ohio State, Illinois, Notre Dame, UC Riverside, the Naval Research Laboratory and Air Force Research Laboratory.
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The project addresses basic research issues in a topical area of materials science with high technological relevance. An important feature of the program is the integration of research and education through the training of students in a fundamentally and technologically significant area. The project brings together electrical engineers, material scientists, physicists, computer scientists, experimentalists, and theoreticians for the purpose of realizing advanced nanostructured quantum dot devices. The project is designed to develop strong technical, communication, and organizational/management skills in students through unique educational experiences made possible by a forefront research environment. There will be active involvement of undergraduates in the program with an emphasis on developing effective oral and written communication skills. Cross-disciplinary research and site visits to each other will enhance the educational process. The project is co-supported by the DMR/EM and ECS/EPDT Divisions/Programs.
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PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
Chung, SY; Jin, N; Berger, PR; Yu, RH; Thompson, PE; Lake, R; Rommel, SL; Kurinec, SK. "Three-terminal Si-based negative differential resistance circuit element with adjustable peak-to-valley current ratios using a monolithic vertical integration," APPLIED PHYSICS LETTERS, v.84, 2004, p. 2688-2690.
Chung, SY; Jin, N; Pavlovicz, RE; Berger, PR; Thompson, PE. "Analysis of the voltage swing for logic and memory applications in Si/SiGe resonant interband tunnel diodes grown by molecular beam epitaxy," IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.6, 2007, p. 158-163.
Chung, SY; Jin, N; Pavlovicz, RE; Berger, PR; Yu, RH; Fang, ZQ; Thompson, PE. "Annealing of defect density and excess currents in Si-based tunnel diodes grown by low-temperature molecular-beam epitaxy," JOURNAL OF APPLIED PHYSICS, v.96, 2004, p. 747-753.
Chung, SY; Jin, N; Rice, AT; Berger, PR; Yu, RH; Fang, ZQ; Thompson, PE. "Growth temperature and dopant species effects on deep levels in Si grown by low temperature molecular beam epitaxy," JOURNAL OF APPLIED PHYSICS, v.93, 2003, p. 9104-9110.
Chung, SY; Park, SY; Daulton, JW; Yu, RH; Berger, PR; Thompson, PE. "Integration of Si/SiGe HBT and Si-based RITD demonstrating controllable negative differential resistance for wireless applications," SOLID-STATE ELECTRONICS, v.50, 2006, p. 973-978.
Hobart, KD; Thompson, PE; Rommel, SL; Dillon, TE; Berger, PR; Simons, DS; Chi, PH. ""p-on-n" Si interband tunnel diode grown by molecular beam epitaxy," JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, v.19, 2001, p. 290-293.
Jin, N; Berger, PR; Rommel, SL; Thompson, PE; Hobart, KD. "pnp Si resonant interband tunnel diode with symmetrical NDR," ELECTRONICS LETTERS, v.37, 2001, p. 1412-1414.
Jin, N; Chling, SY; Yu, R; Berger, PR; Thompson, PE. "Improved vertically stacked Si/SiGe resonant interband tunnel diode pair with small peak voltage shift and unequal peak currents," ELECTRONICS LETTERS, v.40, 2004, p. 1548-1550.
Jin, N; Chung, SY; Heyns, RM; Berger, PR; Yu, RH; Thompson, PE; Rommel, SL. "Tri-state logic using vertically integrated Si-SiGe resonant interband tunneling diodes with double NDR," IEEE ELECTRON DEVICE LETTERS, v.25, 2004, p. 646-648.
Jin, N; Chung, SY; Heyns, RM; Berger, PR; Yu, RH; Thompson, PE; Rommel, SL. "Phosphorus diffusion in Si-based resonant interband tunneling diodes and tri-state logic using vertically stacked diodes," MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, v.8, 2005, p. 411-416.
Jin, N; Chung, SY; Rice, AT; Berger, PR; Thompson, PE; Rivas, C; Lake, R; Sudirgo, S; Kempisty, JJ; Curanovic, B; Rommel, SL; Hirschman, KD; Kurinec, SK; Chi, PH; Simons, DS. "Diffusion barrier cladding in Si/SiGe resonant interband tunneling diodes and their patterned growth on PMOS source/drain regions," IEEE TRANSACTIONS ON ELECTRON DEVICES, v.50, 2003, p. 1876-1884.
Jin, N; Chung, SY; Rice, AT; Berger, PR; Yu, RH; Thompson, PE; Lake, R. "151 kA/cm(2) peak current densities in Si/SiGe resonant interband tunneling diodes for high-power mixed-signal applications," APPLIED PHYSICS LETTERS, v.83, 2003, p. 3308-3310.
Jin, N; Chung, SY; Yu, RH; Di Giacomo, SJ; Berger, PR; Thompson, PE. "RF performance and modeling of Si/SiGe resonant interband tunneling diodes," IEEE TRANSACTIONS ON ELECTRON DEVICES, v.52, 2005, p. 2129-2135.
Jin, N; Chung, SY; Yu, RH; Heyns, RM; Berger, PR; Thompson, PE. "The effect of spacer thicknesses on Si-based resonant interband tunneling diode performance and their application to low-power tunneling diode SRAM circuits," IEEE TRANSACTIONS ON ELECTRON DEVICES, v.53, 2006, p. 2243-2249.
Jin, N; Yu, RH; Chung, SY; Berger, PR; Thompson, PE; Fay, P. "High sensitivity Si-based backward diodes for zero-biased square-law detection and the effect of post-growth annealing on performance," IEEE ELECTRON DEVICE LETTERS, v.26, 2005, p. 575-578.
Junno, T; Carlsson, SB; Xu, HQ; Samuelson, L; Orlov, AO; Snider, GL. "Single-electron tunneling effects in a metallic double dot device," APPLIED PHYSICS LETTERS, v.80, 2002, p. 667-669.
Kummamuru, RK; Orlov, AO; Ramasubramaniam, R; Lent, CS; Bernstein, GH; Snider, GL. "Operation of a quantum-dot cellular automata (QCA) shift register and analysis of errors," IEEE TRANSACTIONS ON ELECTRON DEVICES, v.50, 2003, p. 1906-1913.
Kummamuru, RK; Timler, J; Toth, G; Lent, CS; Ramasubramaniam, R; Orlov, AO; Bernstein, GH; Snider, GL. "Power gain in a quantum-dot cellular automata latch," APPLIED PHYSICS LETTERS, v.81, 2002, p. 1332-1334.
Lake, R; Yang, JJ. "A physics based model for the RTD quantum capacitance," IEEE TRANSACTIONS ON ELECTRON DEVICES, v.50, 2003, p. 785-789.
Orlov, AO; Kummamuru, R; Ramasubramaniam, R; Lent, CS; Bernstein, GH; Snider, GL. "A two-stage shift register for clocked quantum-dot cellular automata," JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v.2, 2002, p. 351-355.
Park, SY; Chung, SY; Yu, R; Berger, PR; Thompson, PE. "Low sidewall damage plasma etching using ICP-RIE with HBr chemistry of Si/SiGe resonant interband tunnel diodes," ELECTRONICS LETTERS, v.42, 2006, p. 719-721.
Park, SY; Yu, R; Chung, SY; Berger, PR; Thompson, P; Fay, P. "Sensitivity of Si-based zero-bias backward diodes for microwave detection," ELECTRONICS LETTERS, v.43, 2007, p. 295-296.
Rivas, C; Lake, R. "Non-equilibrium Green function implementation of boundary conditions for full band simulations of substrate-nanowire structures," PHYSICA STATUS SOLIDI B-BASIC RESEARCH, v.239, 2003, p. 94-102.
Rivas, C; Lake, R; Frensley, WR; Klimeck, G; Thompson, PE; Hobart, KD; Rommel, SL; Berger, PR. "Full band modeling of the excess current in a delta-doped silicon tunnel diode," JOURNAL OF APPLIED PHYSICS, v.94, 2003, p. 5005-5013.
Rivas, C; Lake, R; Klimeck, G; Frensley, WR; Fischetti, MV; Thompson, PE; Rommel, SL; Berger, PR. "Full-band simulation of indirect phonon assisted tunneling in a silicon tunnel diode with delta-doped contacts," APPLIED PHYSICS LETTERS, v.78, 2001, p. 814-816.
Sandu, T; Lake, R; Kirk, WP. "The effect of interface quality on Si/SiO2 resonant tunnel diodes," SUPERLATTICES AND MICROSTRUCTURES, v.30, 2001, p. 201-204.
Snider, GL; Samuelson, L; Sakaki, H. "Special issue on nanoelectronics," IEEE TRANSACTIONS ON ELECTRON DEVICES, v.50, 2003, p. 1821-1822.
Thompson, PE; Hobart, KD; Twigg, ME; Rommel, SL; Jin, N; Berger, PR; Lake, R; Seabaugh, AC; Chi, P. "Epitaxial Si-based tunnel diodes," THIN SOLID FILMS, v.380, 2000, p. 145-150.
Weaver, BD; Thompson, PE; Jin, N; Chung, SY; Rice, AT; Berger, PR. "Radiation tolerance of Si/Si0.6Ge0.4 resonant interband tunneling diodes," JOURNAL OF APPLIED PHYSICS, v.95, 2004, p. 6406-6408.
Word, MJ; Adesida, I; Berger, PR. "Nanometer-period gratings in hydrogen silsesquioxane fabricated by electron beam lithography," JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, v.21, 2003, p. L12-L15.
Yadavalli, KK; Anderson, NR; Orlova, TA; Orlov, AO; Snider, GL; Elam, J. "Single electron memory devices utilizing Al2O3 tunnel oxide barriers," JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, v.22, 2004, p. 3119-3123.
Yadavalli, KK; Orlov, AO; Snider, GL; Elam, J. "Aluminum oxide tunnel barriers for single electron memory devices," MICROELECTRONICS JOURNAL, v.36, 2005, p. 272-276.
Yadavalli, KK; Orlov, AO; Snider, GL; Korotkov, AN. "Single electron memory devices: Toward background charge insensitive operation," JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, v.21, 2003, p. 2860-2864.
Yoon, WJ; Chung, SY; Berger, PR; Asar, SM. "Room-temperature negative differential resistance in polymer tunnel diodes using a thin oxide layer and demonstration of threshold logic," APPLIED PHYSICS LETTERS, v.87, 2005.
Zheng, Y; Lake, R. "Self-consistent transit-time model for a resonant tunnel diode," IEEE TRANSACTIONS ON ELECTRON DEVICES, v.51, 2004, p. 535-541.
Zheng, Y; Lake, R. "Barrier asymmetry and the mm-wave performance of resonant tunnel diodes," SUPERLATTICES AND MICROSTRUCTURES, v.34, 2003, p. 355-360.
Zheng, Y; Rivas, C; Lake, R; Alam, K; Boykin, TB; Klimeck, G. "Electronic properties of silicon nanowires," IEEE TRANSACTIONS ON ELECTRON DEVICES, v.52, 2005, p. 1097-1103.
