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Award Abstract #0541278
CMOS VLSI Design of Low Power Scalable Heterogeneous Networks for Multi-Core Systems-on-Chip
| NSF Org: |
CCF
Division of Computer and Communication Foundations
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| Initial Amendment Date: |
May 19, 2006 |
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| Latest Amendment Date: |
May 7, 2009 |
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| Award Number: |
0541278 |
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| Award Instrument: |
Continuing grant |
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| Program Manager: |
Sankar Basu
CCF Division of Computer and Communication Foundations
CSE Directorate for Computer & Information Science & Engineering
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| Start Date: |
June 1, 2006 |
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| Expires: |
May 31, 2010 (Estimated) |
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| Awarded Amount to Date: |
$281000 |
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| Investigator(s): |
Luca Carloni luca@cs.columbia.edu (Principal Investigator)
Kenneth Shepard (Co-Principal Investigator)
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| Sponsor: |
Columbia University
2960 Broadway
NEW YORK, NY 10027 212/854-6851
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| NSF Program(s): |
SOFTWARE & HARDWARE FOUNDATION,
COMPUTING PROCESSES & ARTIFACT
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| Field Application(s): |
0000912 Computer Science
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| Program Reference Code(s): |
HPCC, 9251, 9218, 7352
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| Program Element Code(s): |
7798, 7352
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ABSTRACT
Proposal no: 0541278.
Luca Carloni
Kenneth Shepard (co-PI)
Columbia University
Title: CMOS VLSI Design of Low-Power Scalable Heterogeneous Networks for Multi-Core Systems-on-Chip.
During the past decade, interconnects have replaced transistors as the dominant determiner of integrated circuit performance by imposing primary limits on latency, energy dissipation, signal integrity and design productivity for giga-scale integration. Low-latency, low-energy circuits for communications will require regular, structured interconnect to engineer wires and tune circuits to those wires. On-chip networks (OCN)
provide such a structured fabric in which communication is obtained by routing packets through a general-purpose interconnect structure rather than using a design-specific ad hoc global wiring network routed by CAD tools. The PIs will investigate the design of scalable OCNs for multi-core systems-on-chip by combining a new low-latency, low-energy, current-mode signalling approach based on damping
compensation with the design of latency-insensitive communication protocols extended to support fault-tolerant communication as well as dynamic voltage and frequency scaling and power-down for the cores.
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