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Award Abstract #0811012
CPA-CSA: Photonic Interconnection Networks for Chip-Multiprocessor Computing Systems
| NSF Org: |
CCF
Division of Computer and Communication Foundations
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| Initial Amendment Date: |
June 16, 2008 |
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| Latest Amendment Date: |
August 19, 2009 |
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| Award Number: |
0811012 |
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| Award Instrument: |
Continuing grant |
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| Program Manager: |
Chitaranjan Das
CCF Division of Computer and Communication Foundations
CSE Directorate for Computer & Information Science & Engineering
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| Start Date: |
July 1, 2008 |
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| Expires: |
June 30, 2011 (Estimated) |
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| Awarded Amount to Date: |
$400000 |
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| Investigator(s): |
Luca Carloni luca@cs.columbia.edu (Principal Investigator)
Keren Bergman (Co-Principal Investigator)
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| Sponsor: |
Columbia University
2960 Broadway
NEW YORK, NY 10027 212/854-6851
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| NSF Program(s): |
COMPUTER SYSTEMS ARCHITECTURE,
SPECIAL PROJECTS - CCF,
INFORMATION TECHNOLOGY RESEARC
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| Field Application(s): |
0000912 Computer Science
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| Program Reference Code(s): |
HPCC, 9218
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| Program Element Code(s): |
4715, 2878, 1640
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ABSTRACT
The impact of communication on the performance of computer systems continues to
grow both at the macro-level for blade servers and clusters of computers, and
at the micro-level in multi-core processors. Meanwhile the tight on-chip power
dissipation constraints have forced practically all major semiconductor
companies to move to multi-core or chip multiprocessor (CMP) architectures.
The emergence of CMPs has in turn placed increased challenges on the
communications infrastructure as the growing number of processing cores
integrated on each chip exacerbates the bandwidth requirements for both
intra-chip and inter-chip communication.
This research aims to harness the recent extraordinary advances in
nanoscale silicon photonic technologies for developing optical interconnection
networks that address the critical bandwidth and power challenges of future
CMP-based system. The insertion of photonic interconnection networks essentially changes the power scaling rules: once a photonic path is established, the data are transmitted end-to-end without the need for repeating, regeneration or buffering. This means that the energy for generating and receiving the data is only expended once per communication transaction anywhere across the computing system. The PIs will investigate the complete cohesive design of an on-chip optical interconnection network that employs nanoscale CMOS photonic devices and enables seamless off-chip communications to other CMP computing nodes and to external memory. System-wide optical interconnection network architectures will be specifically studied in the context of stream processing models of computation.
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