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Award Abstract #1318497

TWC: Small: New Directions in Field Programmable Gate Arrays (FPGA) Security

NSF Org: CNS
Division Of Computer and Network Systems
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Initial Amendment Date: September 9, 2013
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Latest Amendment Date: September 9, 2013
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Award Number: 1318497
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Award Instrument: Standard Grant
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Program Manager: Ralph Wachter
CNS Division Of Computer and Network Systems
CSE Direct For Computer & Info Scie & Enginr
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Start Date: October 1, 2013
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End Date: September 30, 2017 (Estimated)
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Awarded Amount to Date: $432,214.00
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Investigator(s): Russell Tessier tessier@ecs.umass.edu (Principal Investigator)
Christof Paar (Co-Principal Investigator)
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Sponsor: University of Massachusetts Amherst
Research Administration Building
AMHERST, MA 01003-9242 (413)545-0698
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NSF Program(s): Secure &Trustworthy Cyberspace
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Program Reference Code(s): 7434, 7923
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Program Element Code(s): 8060

ABSTRACT

Field-programmable gate arrays (FPGAs) represent an important computing infrastructure which must be protected from attackers. They are used in a wide variety of applications, including networking routers, satellites, military equipment, and automobiles, among others. The storage of FPGA programming information in memory external to the device creates a natural security weakness which, to date, has primarily been addressed via bitstream encryption. Recent work has shown that bitstream encryption is not impervious to attack and, with sufficient effort, the logical function of some or all of an FPGA design can be determined from a bitstream. This work systematically investigates advanced attacks on FPGA designs and, more importantly, develops sound countermeasures against FPGA design manipulations by determined attackers. To eliminate weaknesses, FPGA security is addressed from a new angle: the use of hardware obfuscation to make the true functionality of an FPGA design nearly indecipherable even if the entire logic-level design can be determined by bitstream reverse engineering. These questions are addressed by first developing a series of search-based computer-aided design tools which can identify security primitives (e.g. crypto primitives) in FPGA design logic-level netlists. As a result of this work, a series of automated tools which allow FPGA circuit designers to obscure the functionality of their subcircuits will be developed. These tools will make malicious design modification significantly more difficult or impossible.


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Marc Fyrbiak, Phillip Koppe, Pawel Swierczynski, and Christof Paar. "FPGA Trojans through Detecting and Weakening of Cryptographic Primitives," IEEE Transactions on Computer-Aided Design of Electronic Systems, v.34, 2015.

 

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