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Award Abstract #1321163

SHF:Small:Fine-Grain Many-Core Processor Arrays for Efficient Enterprise Computing

NSF Org: CCF
Division of Computing and Communication Foundations
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Initial Amendment Date: September 23, 2013
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Latest Amendment Date: September 23, 2013
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Award Number: 1321163
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Award Instrument: Standard Grant
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Program Manager: Tao Li
CCF Division of Computing and Communication Foundations
CSE Direct For Computer & Info Scie & Enginr
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Start Date: October 1, 2013
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End Date: September 30, 2016 (Estimated)
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Awarded Amount to Date: $400,000.00
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Investigator(s): Bevan Baas bbaas@ucdavis.edu (Principal Investigator)
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Sponsor: University of California-Davis
OR/Sponsored Programs
Davis, CA 95618-6134 (530)754-7700
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NSF Program(s): COMPUTER ARCHITECTURE
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Program Reference Code(s): 7923, 7941
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Program Element Code(s): 7941

ABSTRACT

Data centers worldwide use approximately 30 billion watts of electricity

with data centers in the United States using approximately 8 to 10

billion watts. Power consumption of datacenter systems is expected to

continue to grow both absolutely and as a percentage of national

consumption. The goal of the proposed research is to develop massively

parallel processor arrays that work in conjunction with traditional

enterprise-class processors to compute datacenter workloads with vastly

greater efficiency. The proposed research may lead to new applications

and capabilities that were previously constrained by power dissipation

or processing throughput.

Project participants will propose, model, develop, and characterize

novel fine-grain many-core architectures, VLSI chip designs, and

application algorithms for a processor array serving as a co-processor

or functional unit. The proposed programmable fine-grained many-core

processor array contains no algorithm-specific hardware and is of a core

granularity that is very lightly explored in prior work. The array will

operate inside or near, and in co-ordination with a host

enterprise-class processor and compute key computational kernels often

with similar or higher performance than the host processor, but with

orders of magnitude higher energy efficiency. During kernel computation,

the host processor could attend to other tasks or enter a low power

state. The targeted workloads include sorting, regular expression based

pattern matching, encryption, data compression, video encoding and

decoding, and other enterprise workloads of high impact that are

discovered during the course of the research.


PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

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Mohammad H. Foroozannejad, Matin Hashemi, Alireza Mahini, Bevan M. Baas, and Soheil Ghiasi. "Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms," IEEE Transactions on Computer-Aided Design of Integrated Circuit Circuits and Systems, v.33, 2014, p. 752.

Bin Liu, Brent Bohnenstiehl, and Bevan M. Baas. "Scalable Hardware-Based Power Management for Many-Core Systems," IEEE Asilomar Conference on Signals, Systems and Computers, 2014.

Bin Liu, Mohammad H. Foroozannejad, Soheil Ghiasi and Bevan M. Baas. "Optimizing Power of Many-Core Systems by Exploiting Dynamic Voltage, Frequency and Core Scaling," IEEE International Midwest Symposium on Circuits and Systems, 2015.

Jon Pimentel and Bevan M. Baas. "Hybrid Floating-Point Modules with Low Area Overhead on a Fine-Grained Processing Core," IEEE Asilomar Conference on Signals, Systems and Computers, 2014.

 

Please report errors in award information by writing to: awardsearch@nsf.gov.

 

 

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