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National Science Foundation HomeNational Science Foundation - Directorate for Computer & Information Science & Engineering (CISE)
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CISE - CCF

SOFTWARE AND HARDWARE FOUNDATIONS (SHF)

The SHF program seeks proposals addressing foundational computer science and engineering research and education to enable and advance the design, analysis, use and evolution of software and hardware. Broad categories of interest within SHF include, but are not limited to:

  • Innovative, transformative ideas that rethink the science and engineering of software, hardware and computer systems; Use of ideas developed in other fields, e.g., logics and agent-based approaches from AI, experimental computer science, eonomics, etc.
  • Development and use of formal languages, logics, models and methods for representation of and reasoning about programs and other artifacts in the context of software engineering, hardware design, and/or co-design
  • Research on programming language principles, semantics, design and implementation, and use in programming computers and computer-based systems, including domain-specific and general-purpose languages
  • Scientific and engineering basis for usable formal methods
  • Empirical investigations of hypotheses about software development processes.
  • Foundations for software science and engineering in new environments such as cloud computing, web services, and ubiquitous/pervasive computing.
  • Understanding computational limits and their consequences to software synthesis, verification, adaptability, etc.
  • New perspectives on requirements, specifications, architectures, composition, evolution, etc.; reconsideration of the structure and dynamics of software development environments; economics of software development
  • New paradigms and frameworks for designing asynchronous circuits/architectures, 3D homogeneous and heterogeneous architectures; feasibility of layout design by taking into account regularity constraints imposed, for example, by 3D or lithography/self-assembly technologies; Designing for device heterogeneity and fault tolerance
  • New directions in designing on- and off- chip interconnects using silicon, optics, wireless , RF, and CNT for multi-core architectures, SoCs, clusters and more ambitious exascale architectures
  • Design approaches for hybrid systems consisting of MEMS, digital, analog, RF, and other technologies and sensor outputs from a variety of physical sources; design of circuits and architectures with emerging nano-scale devices
  • Fundamental and system level research on high performance, power-aware, and fault-tolerant micro architectures, memory and storage systems in deep submicron technology and other emerging technologies,
  • Understanding the opportunities and limitations in designing scalable multicore architectures, SoC systems, application centric architectures such as network processors, and embedded systems,
  • Pushing the hardware-software co-design envelop for new innovations in vertical design paradigm of computer architectures
  • Understanding the basics of power-aware design, power management and optimization spanning from the device level to circuits to architectures, to compiler, to OS and application level in a multi-objective design space involving performance and dependability, exploration of how power potentially brings in another dimension to the fundamental issues of space-time complexity
  • Understanding and exploiting workload characteristics in designing architectures, designing simulation and analytic evaluation frameworks
  • High-performance hardware and software research and enabling technologies for advancing the state-of-the-art in computational science and engineering; scalable algorithms, new programming models and languages for high-end computing
  • Software and hardware processes and artifacts for design, simulation, benchmarking, tracing, performance measurement and tuning of I/O, file, and storage systems in high-performance computing environments
  • Research in compilers for enabling robust high-performance computer systems, including parallelizing compilers and infrastructure for optimizing compilers for multiple platforms, reconfigurable architectures and heterogeneous multicores
  • Exploiting parallelism at multiple levels and programming models; software and compiler support for mapping and scheduling multiple threads on heterogeneous multicore and multiprocessor systems; explicitly parallel programs, optimizing for both parallelism and locality, guaranteeing safety from potential deadlocks, memory leaks, race conditions and other correctness concerns
  • Compiler techniques for managing on-chip communication, power consumption, temperature and fault tolerance in multicore architectures
  • Exploring complex computing and communication processes in biological systems and bio-inspired ideas in computing and communication systems
  • Research that explores shared principles (e.g., networks and control, information representation and coding, learning and adaptation) that are common to biology and computer science

 

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