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NSF Center for High-Performance Reconfigurable Computing (CHREC)
 University of Florida (lead)
The George Washington University
Brigham Young University
Virginia Tech
Scope: Fundamental research and development in reconfigurable computing for a broad range of industry and government partners with compelling needs in high-speed data and embedded processing.
Center Mission and Rationale
Known as CHREC (pronounced “shreck”), this I/UCRC research center and consortium is devoted to scientific and engineering research in architectures, algorithms, programming, services, and systems for the advancement of multi-paradigm computing with hardware-reconfigurable and parallel processing, spanning special- and general-purpose needs, for a broad range of applications. Four distinct goals have been defined for CHREC: (1) Establish the nation's first multidisciplinary research center in reconfigurable high-performance computing as a basis for long-term partnership and collaboration amongst industry, academe, and government; (2) Directly support the research needs of industry and government partners in a cost-effective manner with pooled, leveraged resources and maximized synergy; (3) Enhance the educational experience for a large set of high-quality graduate and undergraduate students; and (4) Advance the knowledge and technologies in this emerging field and ensure relevance of the research with rapid and effective technology transfer.
 High-performance reconfigurable computing, the focus of CHREC, holds tremendous promise in addressing the needs of a broad range of applications, in areas such as signal and image processing, cryptology, communications processing, data and text mining, optimization, bioinformatics, and complex system simulations. Reconfigurable systems may span a variety of platform types, from large-scale machines on earth to mission-critical machines in space. Advantages from a reconfigurable approach can be realized in terms of performance, power, size, cooling, cost, versatility, scalability, and dependability to name a few, important facets where conventional computing infrastructure and technologies are proving unable to meet the needs of an increasing number of challenging and diverse applications.
Research Program
Although a relatively new field, reconfigurable computing (RC) has come to the forefront as a vital and promising paradigm of high-performance processing, often in concert  with conventional microprocessor-based computing. With RC, the full potential of underlying electronics in a system may be better realized in an adaptive manner. At the heart of RC, field-programmable hardware in its many forms has the potential to revolutionize the performance and efficiency of systems for high-end computing as well as deployable embedded computing. One ideal of the RC paradigm is to achieve the performance, scalability, power, and cooling advantages of the “Master of a trade,” a custom-logic hardware device, with the versatility, flexibility, and efficacy of the “Jack of all trades,” a general-purpose processor.
With the objective of realizing the full potential of this field, many research issues much be addressed across a broad spectrum of technical challenges, in terms of new concepts, exploratory designs, analyses, tradeoffs, and insight, from novel device and system architectures to application mapping, performance analysis, and prediction. Many opportunities and challenges exist in advancing and realizing the full potential of reconfigurable technologies. Among the opportunities offered by field-programmable hardware are a high degree of on-chip parallelism that can be mapped directly from dataflow characteristics of the application's defining parallel algorithm, user control over low-level resource definition and allocation, and user-defined data format and precision rendered efficiently in hardware. In exploiting these opportunities, there are many vertical challenges, where we seek to bridge the semantic gap between the high level at which application codes are developed and the low level at which hardware is typically defined. There are also many horizontal challenges, where we seek to integrate or marry diverse resources such as microprocessors, FPGAs, and memory in optimal relationships, in essence bridging the paradigm gap between conventional and reconfigurable processing at various levels in the system and software architectures.
The Center was established as an NSF I/UCRC in 2006.
Facilities and Laboratories
A multidisciplinary suite of leading research laboratories at the four university sites are integrally involved in this center, each with a unique mix of facilities (from development testbeds to supercomputers) that strongly support CHREC activities. These laboratories include:
Center Locations
Headquarters:
CHREC Center Office, 324 Benton Hall, POB 116200, Gainesville , FL 32611-6200
Center home page URL: www.chrec.org
Center Directors:
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