FUNDING > FAILURE-RESISTANT...
Division of Computing and Communication Foundations
FAILURE-RESISTANT SYSTEMS (FRS)
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Important Notice to Proposers
A revised version of the NSF Proposal & Award Policies & Procedures Guide (PAPPG), NSF 13-1, was issued on October 4, 2012 and is effective for proposals submitted, or due, on or after January 14, 2013. Please be advised that, depending on the specified due date, the guidelines contained in NSF 13-1 may apply to proposals submitted in response to this funding opportunity.
Please be aware that significant changes have been made to the PAPPG to implement revised merit review criteria based on the National Science Board (NSB) report, National Science Foundation's Merit Review Criteria: Review and Revisions. While the two merit review criteria remain unchanged (Intellectual Merit and Broader Impacts), guidance has been provided to clarify and improve the function of the criteria. Changes will affect the project summary and project description sections of proposals. Annual and final reports also will be affected.
The National Science Foundation (NSF) and the Semiconductor Research Corporation (SRC) have agreed to embark on a new collaborative research program to address compelling research challenges in failure resistant systems that are of paramount importance to industry, academia, and society at large.
New approaches in the design of electronic circuits and systems are needed for products and services that continue to operate correctly in the presence of transient, permanent, or systematic failures. From large information processing systems supporting communications and computation, to small embedded systems targeting medical and automotive applications, whole industries are facing the challenge of improving the reliability of systems.
Increasing miniaturization and integrated circuit fabrication processes are creating a tension between reliability and efficiency. Higher rates of faults, variation, and degradation due to aging in integrated circuits are forcing systems engineers to assume that devices and circuits may not always perform as designed. More and more, systems are constructed using IP blocks (3rd party Intellectual Property) from different sources, contributing further to unpredictable behavior. Thus behavior under adverse conditions may not be fully known in deployed systems. Current techniques for ensuring reliability, such as voltage and clock rate margins, replication, and disk-based check-pointing will not be able to satisfy the competing requirements for future integrated circuits. These techniques typically operate only at one level of the system stack, yet layers from devices to applications all contribute to system reliability. Such single-layer techniques must be used under worst-case assumptions about the other layers in the stack. This potentially leads to inefficiencies that will make these techniques impractical in future fabrication processes.
A system-level cross-layer approach to reliability, encompassing failure mechanisms of both digital and analog components, has the potential to deliver high reliability with significantly lower power and performance overheads than current single-layer techniques. By distributing reliability across the system design stack, cross-layer approaches can take advantage of the information available at each level, including even application-level knowledge, to efficiently tolerate errors, aging, and variation. This will allow handling of different physical effects at the most efficient stack layer, and can be adapted to varying application needs, operating environments, and changing hardware state.
Fundamental new advances in techniques for designing and developing systems resilient to failure could have a significant impact on multiple industries and boost their competitiveness on a global scale, helping to transform market segments and translate research results into practice.