Award Abstract # 1704834
SHF: Medium: A Cloudless Universal Translator

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
Initial Amendment Date: May 26, 2017
Latest Amendment Date: July 25, 2017
Award Number: 1704834
Award Instrument: Continuing Grant
Program Manager: Danella Zhao
dzhao@nsf.gov  (703)292-4434
CCF  Division of Computing and Communication Foundations
CSE  Direct For Computer & Info Scie & Enginr
Start Date: June 1, 2017
End Date: September 30, 2023 (Estimated)
Total Intended Award Amount: $1,000,000.00
Total Awarded Amount to Date: $1,000,000.00
Funds Obligated to Date: FY 2017 = $1,000,000.00
History of Investigator:
  • David Brooks (Principal Investigator)
     dbrooks@eecs.harvard.edu
  • Paul Whatmough (Co-Principal Investigator)
  • Gu-Yeon Wei (Co-Principal Investigator)
  • Alexander Rush (Co-Principal Investigator)
Recipient Sponsored Research Office: Harvard University
 1033 MASSACHUSETTS AVE 5TH FL
 CAMBRIDGE
 MA  US  02138-5369
(617)495-5501
Sponsor Congressional District: 05
Primary Place of Performance: Harvard University
 33 Oxford Street
 Cambridge
 MA  US  02138-2901
Primary Place of Performance
Congressional District:		 05
Unique Entity Identifier (UEI): LN53LCFJFL45
Parent UEI: ML98SNHE8XL1
NSF Program(s): Software & Hardware Foundation
Primary Program Source: 040100 NSF RESEARCH & RELATED ACTIVIT
Program Reference Code(s): 7924, 7941
Program Element Code(s): 7798
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

This project explores the research foundations necessary to build a universal language translator on a portable computing device for secure private use without the need for reliance on cloud servers. Transformative developments in both machine learning and computer hardware design have made this exciting challenge feasible. The project will nurture a true bidirectional co-design process between researchers in both fields. The broader impacts of the project include: 1) the practical applications of widely available language translation technology, and 2) the training of graduate engineers who have specialization in machine learning as well as hardware and circuit design, skills in broad demand in US industry.

The problem of developing hardware to fit deep learning models is not simply one of fitting current machine learning models on current circuit technology, as the models are much too large, too slow, and too energy-hungry. This project will need to develop novel machine learning techniques that take these factors into account. Machine learning researchers mostly optimize for accuracy; however, the project goal will require considering trade-offs on model size, speed, and computation. Conversely, the hardware design will have to consider and exploit the unique properties of the neural models, such as high-tolerance to certain types of noise, repeated computational structure, and non-linear interactions. The research approach includes three major areas for interaction: model compression, approximation in architecture, and training for unreliable hardware. Succeeding in these goals will be necessary to build a successful on-device system.

PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

Note:  When clicking on a Digital Object Identifier (DOI) number, you will be taken to an external site maintained by the publisher. Some full text articles may not yet be available without a charge during the embargo (administrative interval).

Some links on this page may take you to non-federal websites. Their policies may differ from this site.

Tambe, Thierry and Yang, En-Yu and Ko, Glenn G. and Chai, Yuji and Hooper, Coleman and Donato, Marco and Whatmough, Paul N. and Rush, Alexander M. and Brooks, David and Wei, Gu-Yeon "A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs" IEEE Journal of Solid-State Circuits , 2022 https://doi.org/10.1109/JSSC.2022.3179303 Citation Details
Yang, En-Yu and Jia, Tianyu and Brooks, David and Wei, Gu-Yeon "FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference" International Conference on Application-specific Systems, Architectures and Processors , 2021 https://doi.org/10.1109/ASAP52443.2021.00046 Citation Details
Gupta, Udit M. and Reagen, Brandon and Pentecost, Lillian and Donato, Marco and Tambe, Thierry and Rush, Alexander and Wei, Gu-Yeon and Brooks, David "MASR: A Modular Accelerator for Sparse RNNs" PACT , 2019 10.1109/PACT.2019.00009 Citation Details
Ziegler, Z and Rush, A "Latent Normalizing Flows for Discrete Sequences" International Conference of Machine Learning , 2019 Citation Details
Deng, Y and Kim, Y and Chiu, J and Guo, D and Rush, A "Latent Alignment and Variational Attention" NeurIPS , 2018 Citation Details
Tambe, Thierry and Yang, En-Yu and Ko, Glenn G. and Chai, Yuji and Hooper, Coleman and Donato, Marco and Whatmough, Paul N. and Rush, Alexander M. and Brooks, David and Wei, Gu-Yeon "9.8 A 25mm 2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET" International Solid-State Circuits Conference , 2021 https://doi.org/10.1109/ISSCC42613.2021.9366062 Citation Details
Tambe, Thierry and Hooper, Coleman and Pentecost, Lillian and Jia, Tianyu and Yang, En-Yu and Donato, Marco and Sanh, Victor and Whatmough, Paul and Rush, Alexander M. and Brooks, David and Wei, Gu-Yeon "EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference" MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture , 2021 https://doi.org/10.1145/3466752.3480095 Citation Details

Please report errors in award information by writing to: awardsearch@nsf.gov.

Print this page

Back to Top of page

Top