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Shaving nanoseconds from racing processors

Mark D. Hill

Mark D. Hill, Gene M. Amdahl Professor of Computer Sciences and Electrical & Computer Engineering, University of Wisconsin-Madison

Credit: Bob Rashid. 2006


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graph showing the timeline of technology innovation

Key question: How to advance computer performance without significant technological progress? Hill and others are working to harvest new gains during the "fallow" period of the near future.

Credit: Advancing Computer Systems without Technology Progress, ISAT Outbrief, Mark D. Hill and Christos Kozyrakis, DARPA/ISAT Workshop, March 26-27, 2012


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The computer is one of the most complex machines ever devised and most of us only ever interact with its simplest features. For each keystroke and web-click, thousands of instructions must be communicated in diverse machine languages and millions of calculations computed.

Mark Hill knows more about the inner workings of computer hardware than most. As Amdahl Professor of Computer Science at the University of Wisconsin, he studies the way computers transform 0s and 1s into social networks and eBay purchases, following the chain reaction from personal computer to processor to network hub to cloud and back again.

One of the main ways that Hill does this is by analyzing the performance of computer tasks. Like a coach with a stopwatch, Hill times how long it takes an ordinary processor to, say, analyze a query from Facebook or perform a web search. He's not only interested in the overall speed of the action, but how long each step in the process takes.

Through careful analysis, Hill uncovers inefficiencies, sometimes major ones, in the workflows by which computers operate and creates new solutions that make computers more powerful, more energy efficient and easier to program.

Credit: National Science Foundation


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virtual memory diagram

Software generates virtual addresses as it accesses memory. Each process has its own virtual address space. This virtual address gets mapped to a physical address at the granulairity of the page. The mapping information is stored in a hierarchal page table. Since each memory access needs a translation, processors used a hardware cache called the translation look aside buffer (TLB).

Hits to the TLB are fast but a miss causes a delay of several cycles. The goal is thus to reduce the TLB misses. While such a TLB design remained unchanged for several decades memory usage has changed significantly.

Hill designed a solution that uses paging selectively, adopting a simpler address translation method for key parts of important applications. This reduced the problem, bringing cache misses down to less than 1 percent.

In the age of the nanosecond, fixing such inefficiencies pays dividends. For instance, with such a fix in place, Facebook could buy far fewer computers to do the same workload.

Credit: Mark D. Hill


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makr hill's mecahnical binary adder from a 1974 science fair

Mark Hill's 1974 science fair project--a mechanical binary adder.

Credit: Mark D. Hill


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