NSF/Intel Partnership on Foundational Microarchitecture Research (FoMR)
|Tao Lifirstname.lastname@example.org||(703) 292-8238|
|Yan Solihinemail@example.com||(703) 292-7939|
Important Information for Proposers
ATTENTION: Proposers using the Collaborators and Other Affiliations template for more than 10 senior project personnel will encounter proposal print preview issues. Please see the Collaborators and Other Affiliations Information website for updated guidance.
A revised version of the NSF Proposal & Award Policies & Procedures Guide (PAPPG) (NSF 18-1), is effective for proposals submitted, or due, on or after January 29, 2018. Please be advised that, depending on the specified due date, the guidelines contained in NSF 18-1 may apply to proposals submitted in response to this funding opportunity.
The confluence of transistor scaling, increases in the number of architecture designs per process generation, the slowing of clock frequency growth, and recent success in research exploiting Thread Level Parallelism (TLP) and Data Level Parallelism (DLP) all point to an increasing opportunity for innovative microarchitecture techniques and methodologies in delivering performance growth in the future.
The NSF/Intel Partnership on Foundational Microarchitecture Research will support transformative microarchitecture research targeting improvements in instructions per cycle (IPC). This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of existing microarchitectural structures. Specifically, FoMR seeks to advance research that has the following characteristics: (1) high IPC techniques ranging from microarchitecture to code generation; (2) “microarchitecture turbo” techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation. Advances in these areas promise to provide significant performance improvements to continue the cadence promised by Moore’s Law.