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March 8, 2024

Demonstrating 3D integration on a massive scale

In this rendering, researchers at Penn State demonstrated 3D integration -- vertically stacking multiple layers of semiconductor devices to pack more silicon-based transistors onto a computer chip -- on a massive scale, enabling more energy-efficient computing.

[Research supported by U.S. National Science Foundation grant ECCS 2042154.]

Learn more in the Penn State news story Integrating dimensions to get more out of Moore’s Law and advance electronics. (Date of image: 2024; date originally posted to NSF Multimedia Gallery: March 8, 2024)

Credit: Elizabeth Flores-Gomez Murray/Materials Research Institute, Penn State

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