This document has been archived. Title: NSF-SIA/NRI Graduate Student and Postdoctoral Fellow Supplements to NSF Centers in Nanoelectronics (NSF 06-051) Date: 08/15/06 National Science Foundation 4201 Wilson Boulevard Arlington, Virginia 22230 NSF-SIA/NRI Graduate Student and Postdoctoral Fellow Supplements to NSF Centers in Nanoelectronics (NSF 06-051) Dear Colleague: In 2005,1 the National Science Foundation (NSF) undertook a cooperative effort with the Semiconductor Industry Association (SIA) through the industry's Nanoelectronics Research Initiative (NRI), a consortium of six participating SIA member companies,2 to provide supplemental funding opportunities to NSF Centers involved in long-term nanoelectronics research. The supplemental funding supported additional graduate students and postdoctoral fellows to work in collaborative efforts with participating NRI company assignees on exploring new concepts beyond the scaling limits of CMOS (Complementary Metal Oxide Semiconductor) technology. Such efforts are intended to enhance nanoelectronics research and education, strengthen industry linkages with NSF Centers, and develop future cadres of industry and faculty researchers to help drive the field. The NRI's goal is to encourage exploratory nanoelectronics research at universities on topics with the potential for maintaining the historical scaling of both computational power and cost of information processing (http://www.src.org/nri/default.asp). NSF is leveraging its significant fundamental research investments in nanoelectronics that have been made through both its priority area for Nanoscale Science and Engineering and its core programs (http://www.nsf.gov/crssprgm/nano/). These research investments contribute to the fundamental research base and the creation of new knowledge that are critical to sustaining the U.S. leadership and competitiveness in the global semiconductor industry. NSF and NRI are continuing this cooperative supplement opportunity in 2006. The supplements will support only research that is consistent with the mission of the NSF Centers and has potential to meet the needs of the NRI: discovery of a novel non-charge based logical switch as a successor to CMOS technology; and novel architectures at the limits of or beyond CMOS. NSF and NRI will each provide $1,000,000 in funds, for a total investment of $2,000,000, subject to the availability of funds. This will allow approximately five NSF Centers to receive supplemental awards, in the range of $300,000 to $500,000 total funding each, for a duration of three years. All NSF Centers involved in nanoelectronics research are eligible to apply, including those that were awarded supplements in the 2005 competition. For newly competing NSF Centers, the supplement request should include: (1) summary of the Center's current research in the area of nanoelectronics, and (2) description of the proposed new work on exploratory beyond-CMOS research in which the additional graduate students and/or postdoctoral fellows would be involved. The request must also include a letter of support from the NERC. Early contact with industry via NERC is strongly encouraged. NERC will assign an industry liaison to assist in the development of industry-relevant aspects of the proposed plan. For NSF Centers that were awarded supplements in the 2005 competition,3 the supplement request should include: (1) summary of the Center's current research in the area of nanoelectronics, (2) progress report for the initial supplement period including involvement of industry assignees, and (3) description of the proposed new work on exploratory beyond-CMOS research in which the additional graduate students and/or postdoctoral fellows would be involved. The request must also include a letter of support from the NERC. All supplemental requests should be prepared in accordance with the NSF Grant Proposal Guide (GPG) and submitted via FastLane under the existing award (see GPG Section V, B, 4 for Supplemental Funding Requests; http://www.nsf.gov/publications/pub_summ.jsp?ods_key=gpg). The length of the request should not exceed 6 text pages. Upon submission of the supplement to FastLane, please email confirmation to NSF- NRIsupplement@nsf.gov giving the supplement number assigned by FastLane, the name of the PI and of the NSF Center, and the title of the supplement. This will assure that we accurately track all submissions. The deadline for submission of supplement requests via FastLane is 5 pm local time, November 17, 2006. Supplement requests will be reviewed internally by NSF program officers from the participating Directorates. Award decisions will be made jointly by NSF and NERC on topics of interest to NRI participants consistent with the mission of the respective NSF Centers. NSF and NERC will use their own award mechanisms in jointly funding these supplements. NSF support will be provided up-front as supplemental funding to the existing awards. NRI funds will be awarded as unrestrictive gifts, with no overhead or intellectual property requirements. Annual progress reports on work conducted under the supplemental funding will be submitted jointly to NSF and NERC. A process of joint oversight for the supplemental awards will be established by NSF and NERC. ------------ 1 NSF 05-598 2 NRI is administered by the Nanoelectronics Research Corporation (NERC), a subsidiary of the Semiconductor Research Corporation (SRC). Six SIA member companies are participating in NRI, and in this supplement opportunity: Advanced Micro Devices, Freescale Semiconductor, IBM, Intel, Micron Technology, and Texas Instruments. 3 Network for Computational Nanotechnology (Purdue); MRSEC: Center for Nanoscopic Materials (U Virginia, Notre Dame); NSEC: Columbia Center for Electronic Transport in Molecular nanostructures ( Columbia); MRSEC at UCSB (UC Santa Barbara); NSEC: Science of Nanoscale Systems and their Device Applications (Harvard); and MRSEC: Center for Semiconductor Physics in Nanostructures (U Oklahoma, U Arkansas). Please contact the following officials should you need additional information: * Directorate for Engineering * Lawrence S. Goldberg, E-mail: lgoldber@nsf.gov * Directorate for Mathematical and Physical Sciences * Ulrich Strom, E-mail: ustrom@nsf.gov * Directorate for Computer and Information Science and Engineering * Sankar Basu, E-mail: sabasu@nsf.gov * Nanoelectronics Research Corporation (NERC) * Jeffrey Welser, E-mail: jeff.welser@src.org Sincerely, Richard Buckius Assistant Director for Engineering Judith S.Sunley Acting Assistant Director for Mathematical and Physical Sciences Peter A.Freeman Assistant Director for Computer and Information Science and Engineering