Division of Computing and Communication Foundations
Energy-Efficient Computing: from Devices to Architectures
Important Information for Proposers
ATTENTION: Proposers using the
Collaborators and Other Affiliations template for more than 10
senior project personnel will encounter proposal print preview
issues. Please see the Collaborators
and Other Affiliations Information website for updated guidance.
A revised version of the NSF Proposal & Award Policies & Procedures Guide (PAPPG) (NSF 17-1), is
effective for proposals submitted, or due, on or after January 30, 2017. Please be advised that, depending
on the specified due date, the guidelines contained in NSF 17-1 may apply to proposals submitted in response to this
There is a consensus across the many industries touched by our ubiquitous computing infrastructure that future performance improvements across the board are now severely limited by the amount of energy it takes to manipulate, store, and critically, transport data. While the limits and tradeoffs for this performance-energy crisis vary across the full range of application platforms, they have all reached a point at which evolutionary approaches to addressing this challenge are no longer adequate.
Truly disruptive breakthroughs are now required, and not just from any one segment of the technology stack. Rather, due to the complexity of the challenges, revolutionary new approaches are needed at each level in the hierarchy. Furthermore, simultaneous co-optimization across all levels is essential for the creation of new, sustainable computing platforms.
These simultaneous technical and organizational challenges have never been as complex or as critically important as they are now. The urgency of solving the multi-disciplinary technical challenges will require new methods of collaboration and organization among researchers.
Therefore, a comprehensive and collaborative approach must be undertaken to maximize the potential for successfully identifying and implementing revolutionary solutions to break through the bottleneck of energy-constrained computational performance. Programmers, system architects, circuit designers, chip processing engineers, material scientists, and computational chemists must all explore these new paths together to co-design an optimal solution path.
The National Science Foundation (NSF) and the Semiconductor Research Corporation (SRC) recognize this need, and agree to embark on a new collaborative research program to support compelling research that is of paramount importance to industry, academia and society at large. This partnership will specifically support new research to minimize the energy impacts of processing, storing, and moving data within future computing systems, and will be synergistic with other research activities that address other aspects of this overarching energy-constrained computing performance challenge.
What Has Been Funded (Recent Awards Made Through This Program, with Abstracts)
Map of Recent Awards Made Through This Program